1. Field of the Invention
The invention relates generally to circuits for synchronization of received data and more particularly to a circuit for recovering a data clock pulse from an NRZI coded data stream.
2. Description of the Prior Art
Synchronous transmission of data, i.e. data which is synchronous with a timing signal, is commonly coded in NRZI (non-return to zero inverted) form. In this form, a zero, or low, data state is indicated by a transition in the data stream from low to high or high to low. A one, or high, data state is indicated by the absence of a transition in the data stream. In cases of data transmission using a modem where the data clock is derived or "recovered" from the received data, NRZI coding is typically used to insure that an adequate number of data stream transitions occur for accurate generation of the timing signal.
In addition, "protocols" or generalized techniques of formating and structuring the data to be transmitted have been developed. Two common protocols are Synchronous Data Link Control and the High-level Data Link Control. These techniques vary in some respects, but have many features in common. One of these features is termed "zero insertion", which ensures that, except for specifically designated control characters, no more than five consecutive high signals will be received before a low signal will be seen. In other words, a data stream transition will appear after no more than six bit times.
Synchronous modems typically provide both a transmit clock for use in performing the NRZI encoding and a receive clock for use in decoding the received data. Some modems, however, provide only a transmit clock and lower cost asynchronous modems generally provide neither. Timing for the received data stream in the absence of a receive clock is generally accomplished through use of an analog phase-locked loop. This technique typically compares the transitions in the received data with a source frequency. If they are not coincident, an error voltage is generated which raises or lowers the source frequency, within limits, until the clock is coincident with the data stream transistions.
The phase-locked loop technique has certain disadvantages. For example, individual source frequencies must be generated by discrete components having varying tolerances. Costly components must generally be used to obtain a precise source frequency. In addition, if multiple data frequencies must be supported, separate circuits must typically be used to determine each frequency.
The present invention relates to a novel circuit for recovery of a data clock from an NRZI coded data stream which is free of the above mentioned problems.